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ããŸããããããã£ãŠãã¿ããšæžããã»ãããåè·¯å³ãéããŠèŠããæ°ãããŸãããïŒ 8ã¯ãŒãïŒ16ãã€ãïŒã®RAMãäœã Register ã8å䞊ã¹ãŠRAMãäœããŸãããã骚çµã¿ã¯äžèšã®ãããªã³ãŒãã«ãªããŸãã pub struct RAM8 { registers: [Register; 8] } impl RAM8 { pub fn new() -> Self { Self { registers: [ Register::new(), Register::new(), Register::new(), Register::new(), Register::new(), Register::new(), Register::new(), Register::new(), ]} } pub fn out(&self, address: [bool; 3]) -> Word { ... } pub fn clock(&mut self, address: [bool; 3], input: Word, load: bool) { ... } } Register ãšãã䌌ãŠããŸãããããèŠããš out() ãš clock() ã« address: [bool; 3] ãšããåŒæ°ãæ°ãã«å ãã£ãŠããŸããaddress ã¯èŠããã«ããã€ã³ã¿ã§ããã¬ãžã¹ã¿ã¯8åã§ãããã3bit ã®ã¢ãã¬ã¹ã§äžæã«æå®ããããšãåºæ¥ãŸããout() 㯠address ã§æå®ãããã¢ãã¬ã¹ã®ã¬ãžã¹ã¿ãèªã¿åããŸãããclock() 㯠address ã§æå®ãããã¬ãžã¹ã¿ã®å€ãæžãæãããšããããã§ãã RAM8::out() å®çŸãããã®ã¯ããããåäœã§ãã impl RAM8 { pub fn out(&self, address: [bool; 3]) -> Word { match address { [false, false, false] => self.registers[0].out(), [true, false, false] => self.registers[1].out(), [false, true, false] => self.registers[2].out(), ... [true, true, true ] => self.registers[7].out(), } } } ãã¡ãã match åŒã¯ããºã«ãã§ããããããã䜿ããã«è«çåè·¯ã§åå²ãå®çŸããªããŠã¯ãªããŸããã 1bit ã¬ãžã¹ã¿ã®ãšãã«ã¯ãif åŒã mux() ã«çœ®ãæããã®ã§ãããããã§ã mux() ãçµã¿åãããŠæ¡åŒµããŠãããŸãã ãŸã次ã®ãããªåäœããã mux16() ãšãããã®ãäœããŸãã pub fn mux16(a: Word, b: Word, sel: bool) -> Word { if sel { b } else { a } } ã»ãšãã© mux() ãšåãã«èŠããŸãããå
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ã§ããŸãã pub fn mux16(a: Word, b: Word, sel: bool) -> Word { [ mux(a[ 0], b[ 0], sel), mux(a[ 1], b[ 1], sel), mux(a[ 2], b[ 2], sel), mux(a[ 3], b[ 3], sel), mux(a[ 4], b[ 4], sel), mux(a[ 5], b[ 5], sel), mux(a[ 6], b[ 6], sel), mux(a[ 7], b[ 7], sel), mux(a[ 8], b[ 8], sel), mux(a[ 9], b[ 9], sel), mux(a[10], b[10], sel), mux(a[11], b[11], sel), mux(a[12], b[12], sel), mux(a[13], b[13], sel), mux(a[14], b[14], sel), mux(a[15], b[15], sel), ] } ç¶ããŠã次ã®ãããªåäœããã mux4way16() ãšãããã®ãäœããŸãã pub fn mux4way16(a: Word, b: Word, c: Word, d: Word, sel: [bool; 2]) -> Word { if sel[1] { mux16(c, d, sel[0]) } else { mux16(a, b, sel[0]) } /* 次ã®ã³ãŒããšç䟡 match sel { [false, false] => a, [true, false] => b, [false, true ] => c, [true, true ] => d, } */ } ããã¯äžèšã®å®è£
ã§å®çŸã§ããããšãããåããã§ãããã pub fn mux4way16(a: Word, b: Word, c: Word, d: Word, sel: [bool; 2]) -> Word { mux16(mux16(a, b, sel[0]), mux16(c, d, sel[0]), sel[1]) } åæ§ã«ã㊠mux8way16() ãäœãããšãåºæ¥ãŸãã pub fn mux8way16( a: Word, b: Word, c: Word, d: Word, e: Word, f: Word, g: Word, h: Word, sel: [bool; 3] ) -> Word { mux16( mux4way16(a, b, c, d, [sel[0], sel[1]]), mux4way16(e, f, g, h, [sel[0], sel[1]]), sel[2] ) } ããã䜿ã£ãŠãRAM8::out() ã¯æ¬¡ã®ããã«å®è£
ã§ããŸãã impl RAM8 { pub fn out(&self, address: [bool; 3]) -> Word { mux8way16( self.registers[0].out(), self.registers[1].out(), self.registers[2].out(), self.registers[3].out(), self.registers[4].out(), self.registers[5].out(), self.registers[6].out(), self.registers[7].out(), address) } } 以äžã§ãæå®ããã address ã®ã¬ãžã¹ã¿ãèªã¿åãåè·¯ãäœããŸããã RAM8::clock() address ããã®èªã¿åãã¯åºæ¥ãŸãããããä»åºŠã¯ address ãžã®æžã蟌ã¿ãå®è£
ããŸããããå®çŸãããã®ã¯ããããåäœã§ãã impl RAM8 { pub fn clock(&mut self, address: [bool; 3], input:Word, load: bool) -> Word { match address { [false, false, false] => self.registers[0].clock(address, input, load), [true, false, false] => self.registers[1].clock(address, input, load), [false, true, false] => self.registers[2].clock(address, input, load), ... [true, true, true ] => self.registers[7].clock(address, input, load), } } } ããããã¡ãã£ãšããã¯ç¡çããããŸãããã®ã³ãŒã㯠address ã®å€ã«å¿ããŠã¯ããã¯ä¿¡å·ãå
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¥åãç¶ããªããŠã¯ãªããŸããã ã§ãã®ã§ããããªãµããªæ¹éã«åãæ¿ããŸãã impl RAM8 { pub fn clock(&mut self, address: [bool; 3], input:Word, load: bool) -> Word { let load8: [bool; 8] = match address { [false, false, false] => [load, false, false, false, false, false, false, false], [true, false, false] => [false, load, false, false, false, false, false, false], [false, true, false] => [false, false, load, false, false, false, false, false], ... [true, true, true ] => [false, false, false, false, false, false, false, load], }; self.registers[0].clock(input, load8[0]); self.registers[1].clock(input, load8[1]); self.registers[2].clock(input, load8[2]); self.registers[3].clock(input, load8[3]); self.registers[4].clock(input, load8[4]); self.registers[5].clock(input, load8[5]); self.registers[6].clock(input, load8[6]); self.registers[7].clock(input, load8[7]); } } åžžã«å
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¥åã®äŒç·ããããããããã§ååããããšãåºæ¥ãŸããã ã§ã¯ä»ãŸã§ãšåæ§ã«ãif ã match ã䜿ã£ãŠããç®æïŒload8 ãæ±ããŠããç®æïŒãè«çåè·¯ã«çœ®ãæããŠãããŸãããã ãŸã DMux ïŒDemultiplexorïŒãšããçŽ åãäœããŸããããã¯æ¬¡ã®ãããªåäœããããã®ã§ãã pub fn dmux(input: bool, sel: bool) -> [bool; 2] { match sel { false => [input, false], true => [false, input], } } ããã¯æ¬¡ã®ãããªè«çåè·¯ã§å®çŸã§ããŸãã pub fn dmux(input: bool, sel: bool) -> [bool; 2] { [and(input, not(sel)), and(input, sel)] } ãããçµã¿åãããŠã次ã®åäœä»æ§ã® dmux4way() dmux8way() ãäœããŸãã pub fn dmux4way(input: bool, sel: [bool; 2]) -> [bool; 4] { match sel { [false, false] => [input, false, false, false], [true, false] => [false, input, false, false], [false, true ] => [false, false, input, false], [true, true ] => [false, false, false, input], } } pub fn dmux8way(input: bool, sel: [bool; 3]) -> [bool; 8] { match sel { [false, false, false] => [input, false, false, false, false, false, false, false], [true, false, false] => [false, input, false, false, false, false, false, false], [false, true, false] => [false, false, input, false, false, false, false, false], ... [true, true, true ] => [false, false, false, false, false, false, false, input], } } ããããã match åŒãé€å»ããŠè«çåè·¯ãšããŠã©ãå®è£
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ã§ããŸãã impl RAM8 { pub fn clock(&mut self, address: [bool; 3], input: Word, load: bool) { let load = dmux8way(load, address); self.registers[0].clock(input, load[0]); self.registers[1].clock(input, load[1]); self.registers[2].clock(input, load[2]); self.registers[3].clock(input, load[3]); self.registers[4].clock(input, load[4]); self.registers[5].clock(input, load[5]); self.registers[6].clock(input, load[6]); self.registers[7].clock(input, load[7]); } } ãããã« ãã®ããšã¯ãRAM8 ã8å䞊ã¹ãŠçµã¿åãã㊠RAM64 ãäœããRAM64 ã8å䞊ã¹ãŠ RAM512 ãäœãâŠããšç¶ããŠRAMã倧ããããŠãããŸãã ãããŠãCPUãè«çã²ãŒããšã¬ãžã¹ã¿ã®çµã¿åããããæ§æããCPUãšRAMãç¹ããŠãROMããæ©æ¢°èªã³ãŒããèªã¿åºããŠå®è¡ããããã«ããŠãããŸãã ãããçµã¿äžãã£ãŠåãããšããäœãšãèšããªãæåãèŠãããã®ã§ããç¹ã«ã¬ãžã¹ã¿ãRAMåšãã®ä»çµã¿ã«ã¯ã¯ã¯ã¯ããŸãããã³ã³ãã¥ãŒã¿ãšããã®ã¯ãã¯ããã¯ä¿¡å·ã§ã«ãã«ããšåããŠãã壮倧ãªãã¿ãŽã©è£
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ãã¶ãã«åããããšãããåããªãâŠã ä»ã¡ãã£ãšåå ã調ã¹ãæéãåããªãã®ã§ããããŸãããããµãæãã®çµããæ¹ã«ãªããŸãããã以äžã§ãã The post Rustã§RAMã®åäœåçãã·ãã¥ã¬ãŒããã appeared first on CADDi Tech Blog.